1. Field of the Invention
The present invention relates to analog-digital converters, in particular to successive approximation register (SAR) analog-digital converters and measures to increase their speed without sacrificing power efficiency.
2. Description of Related Art
SAR converters are frequently used in integrated CMOS devices since they provide a reasonable resolution and conversion time and can be implemented by optimally utilizing the advantages of the CMOS technology, which are small-sized switches and capacitors having well-defined relative capacitances. SAR converters generally include at least one capacitor array with capacitors of different values forming a 2C-C network or forming a capacitance ladder with capacitance values having a relation of a factor of 2n (n: number of stages) between one another.
The capacitors of the capacitor array are charged by connecting them to a signal line carrying the input signal to be converted. The capacitor array is connected to a latch which serves for comparing a potential stored in the capacitor array to a reference potential in a sampling phase. The comparison result is stored in a shift register. Based on the comparison result of the previous sampling phase, a switching of a capacitor of the capacitor array is performed to increase or decrease the potential stored in the capacitor array.
In a different kind of SAR analog-digital converter a switching associated to a respective capacitance in the capacitor array is performed prior to comparing the stored potential to the reference potential and based on the comparison result the switching state of the last switching is maintained as it is or is switched back to the original switching state.
The performance characteristics of an SAR analog-digital converter are generally related to power consumption, conversion precision, and conversion speed. Improving one of these characteristics often requires a compromise as the other performance characteristics are affected. For instance, for converters with a very fast capacitor settling speed, the delay of the logic and capacitor settling can be shorter than the latch reset time. With respect to the conversion speed the operation of the decision latch becomes a limiting factor since after each conversion step the decision latch has to be reset to keep the conversion offset low and to maintain the conversion precision.
While the reset time is significantly longer than the times that are needed for processing of the latch results and the adjusting of the latch input voltage by switching a respective switch in the capacitor array, the reset time is critical and substantially contributes to the latch cycle period of the analog-digital converter.
Document WO 2010/044000 A1 discloses an analog-digital converter having two subconverters which are operated in an interleaved manner, wherein a track-and-hold stage on the input side of the capacitor array is shared to eliminate calibration issues.
Document S. G. Talekar and S. Ramasamy, “A Low Power 700MSPS 4 bit Time Interleaved SAR ADC in 0.18 μm CMOS”, TENCON 2009, discloses an analog-digital converter with multiple comparators. The multiple comparators are operable to convert more than 1 Bit per comparison step.
Document T. Jiang et al., “Single channel, 1.25-GS/s, 6-Bit, Loop-Unrolled Asynchronous SAR-ADC in 40 nm-CMOS”, IEEE 2010, discloses an analog-digital converter having a number of latches corresponding to the number of bits of the conversion. This results in an increased calibration time and complexity for each of the decision latches, so that the benefit concerning speed is minimal. Furthermore, the total area for implementing the decision latches in an integrated manner is significant.